{SAP JOBS USA:114310} Req Validation Engineers with System Verilog expertise

Validation Engineers with SystemVerilog expertise

18 months
Folsom(CA)


Relevant Experience
(in Yrs)4-6 years only
Technical/Functional SkillsMust Have:
-Experience in defining, implementing and deploying verification capabilities and methodologies
-Expertise in SystemVerilog,  Perl scripting, and VCS simulator
-Strong experience with architecting optimized validation environments, testplan/testbench/bus-functional-models/checkers/trackers/functional coverage development, and test writing/debug
-Working knowledge of UNIX, and Windows
-AVM knowledge
Good to have:
-Familiarity with Graphics concepts, credit-based protocols, power-management flows
-Experience with Java and C/C++ is a plus
Experience Required4-6 years only
Roles & Responsibilities
EducationElectrical or Mechanical Engineer

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