Friday, 7 June 2013

{SAP JOBS USA:119150} Job l Opening For Verilog - 6 Months + @ Folsom, CA

Hi,

This is Arun from Agile Enterprise Solutions.

This is in reference to the following position.

 

Please reply with resume, Rate and contact details ASAP

 

Job Title

Verilog

Location

Folsom, CA

Duration

6 Months +

Primary Skills

verilog/VHDL

 

Job Description

o Hands on knowledge of System Verilog.
o Hands on working knowledge of methodologies like VMM, OVM, eRM
o Strong hands-on experience on SOC projects.
o Good experience in Full chip SOC and unit level validation.
o Good knowledge of digital design concepts
o Good knowledge of ASIC design flow
o Hands on knowledge of complete ASIC Front-end verification flow – Verification planning to closure.
o Good knowledge of Verilog/VHDL
o Experience in defining verification plan
o Experience in building re-usable verification environment
o Understand the concept of random test generation and coverage
o Experience on coverage points and SV assertion
o Good team player and ability to work with  stakeholders like RTL team, DFT team and Physical Design team
o Good hands on knowledge of Gate level  simulations (with back annotated delay values)
o Good hands on knowledge of Planning and execution of IP level and fullchip verification

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Thanks & Regards
Arun Alampally
Agile Enterprise Solutions
Inc || "Ensuring Client's Success" ||
630-242-6423 Ext:205 - Work
630-206-2397
- Fax
E-mail : arun_alampally@aesinc.us.com
yahoo! : arun.recruitment

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